1. Field of the Invention
The embodiments discussed herein are related to a semiconductor device.
2. Description of the Related Art
Insulated gate bipolar transistors (IGBT) have an advantage of low ON resistance consequent to the effects of conductivity modulation. Conventionally, to efficiently facilitate low ON resistance by the effects of conductivity modulation, an IGBT is commonly known in which a carrier storage (CS) layer that is of the same conductivity type as the drift layer and has a higher impurity concentration than the drifter layer, is disposed at a base front surface side inside the drift layer. The carrier storage layer becomes a barrier of minority carriers and the minority carrier storage effect becomes high, whereby current density between the collector and emitter increases and the conductivity modulation effect increases.
Further, concerning metal oxide semiconductor field effect transistors (MOSFET), a technique of facilitating low ON resistance by increasing the impurity concentration of a portion that is near a channel and on a base front surface side inside the drift layer is commonly known. In a MOSFET, a CS layer disposed at a base front surface side inside the drift layer functions as a carrier spread layer, and so-called junction FET (JFET) resistance decreases and ON resistance drops. Hereinafter, the carrier storage layer and the carrier spread layer will be collectively referred to as “CS layer”.
Concerning the structure of a semiconductor device that has a CS layer, an IGBT of a planar gate structure will be described. FIG. 9 is a cross-sectional view of a structure of an edge termination structure of a conventional semiconductor device that has a CS layer. An edge termination structure 122 is disposed at an outer side of an active region 121, is a region that surrounds the active region 121, and has a function of relaxing the electric field of an n−-type drift layer 102 at a base front surface side to maintain the breakdown voltage. The active region 121 is a region in which current flows during an ON state. As depicted in FIG. 9, a conventional semiconductor device is created using an epitaxial base formed by the n−-type drift layer 102, an n-type CS layer 103, and a p+-type base layer 104 that are epitaxially grown and sequentially stacked on a front surface of a p+-type semiconductor substrate 101. In other words, the n-type CS layer 103 is disposed between the n−-type drift layer 102 and the p+-type base layer 104.
Further, the n-type CS layer 103 is disposed from the active region 121, across the edge termination structure 122. In the edge termination structure 122, a groove 113 is disposed that penetrates the p+-type base layer 104 in a direction of depth and reaches the n-type CS layer 103. A junction termination extension (JTE) structure that abuts an end portion of the p+-type base layer 104 is disposed at a portion the n-type CS layer 103, the portion exposed at a bottom of the groove 113. The JTE structure is formed by a p-type region (first and second JTE regions 114, 115) that has a lower impurity concentration than the p+-type base layer 104. Reference numerals 107, 110, and 112 denote a p++-type contact region, an interlayer insulating film, and a collector electrode, respectively.
As a device that facilitates low ON resistance by disposing a CS layer in such a manner, a MOS-type semiconductor device of a drain gate structure produced (manufactured) using a semiconductor that has a wider bandgap than silicon (Si) (hereinafter, wide-bandgap semiconductor) has been proposed (for example, refer to Japanese Patent Application Laid-Open Publication No. 2008-16747 (paragraphs 0018 to 0019 and FIG. 5), Japanese Patent No. 5444608 (paragraphs 0016 to 0017 and FIGS. 1, 2), and Japanese Patent No. 5054255 (line 32 of page 14 to line 14 of page 15 and FIG. 20)). In Japanese Patent Application Laid-Open Publication No. 2008-16747, and Japanese Patent Nos. 5444608 and 5054255, a CS layer formed from an epitaxial layer is disposed inside the drift layer, near an interface with the base layer and at a depth that from the base front surface, is shallower than the trench bottom portion.
In particular, when a semiconductor device is produced (manufactured) using a wide-bandgap semiconductor such as silicon carbide (SiC), since the control of the impurity concentration and thickness is relatively easy, deposition of the CS layer by epitaxial growth is common such as in Japanese Patent Application Laid-Open Publication No. 2008-16747, and Japanese Patent Nos. 5444608 and 5054255. However, in such cases, the CS layer is further formed in the edge termination structure surrounding the active region. When the CS layer is formed in the edge termination structure, the impurity concentration of the CS layer may become 10 to several 100 times greater than that of the drift layer, whereby the JTE structure disposed in the edge termination structure may be adversely affected and the maximum breakdown voltage of the edge termination structure may drop. The breakdown voltage of the overall device drops consequent to the maximum breakdown voltage of the edge termination structure dropping.